Senior Digital Design RTL Engineer
| Company | PDDN |
|---|---|
| Location | Santa Clara, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Expert or higher |
Requirements
- 10+ years of experience in RTL design using Verilog/System Verilog
- Skilled in developing micro-architectural documentation
- Skilled in quality checks
- Skilled in integration support for SoC designers
Responsibilities
- Develop micro-architectural documentation
- Perform quality checks
- Provide integration support for SoC designers
Preferred Qualifications
- Python scripting
- Low power design (UPF/CPF)
- Familiarity with Synopsys/Cadence tools