Senior Engineer II-Design – Functional Verification
| Company | Microchip Technology |
|---|---|
| Location | Allentown, PA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Senior, Expert or higher |
Requirements
- Minimum BSEE and of 8 years related proven verification or silicon design experience
- RTL verification using coverage driven verification techniques
- Scripting in any language
- Proficient in HDL languages SystemVerilog, Verilog or VHDL
- Familiarity with UNIX environment
- Good analytical, oral and written communication skills
- Able to write clean, readable, and maintainable code
- Self-motivated, proactive team player
Responsibilities
- Defining verification plans and building verification environments for chip/module level designs using System Verilog with UVM
- Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification
- Simulations using Cadence Incisive Enterprise Simulator, and debugging using SimVision
- Writing test cases, checkers and coverage that implement the verification test plan
- Support emulation, ASIC lab validation including lab debug and providing root-cause simulations and workarounds
Preferred Qualifications
- Programming experience or coursework in C, C++
- Experience or academic knowledge of the design and verification of interfaces and controllers for high speed serial protocols such as Serial Attached SCSI, Serial ATA, and PCI-Express
- Understanding of ASIC designs and verification methodologies
- Knowledge of MIPS or ARM, X86 system architecture