Senior Microarchitect – Memory Coherency Fabric Systems

Senior Microarchitect – Memory Coherency Fabric Systems

Requirements

• Graduate of Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with at least 4+ years’ experience in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding OR;
• Graduate of Master’s Degree in Electrical Engineering, Computer Engineering, or a related field with at least 3+ years’ experience in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding OR;
• PhD in Electrical Engineering, Computer Engineering, or a related field.
• Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI).
• Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures).
• Proven RTL coding experience in Verilog or SystemVerilog.
• Proficiency in simulation tools for performance modeling and analysis.
• Familiarity with physical design implications of memory fabric architectures (timing, power, area).
• Experience with EDA tools for synthesis, linting, and static timing analysis.

Responsibilities

• Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
• Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
• Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.
• Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.
• Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.
• Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.
• Mentor junior engineers and contribute to technical reviews and design documentation.
• Stay updated with emerging technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware.

Preferred Qualifications

• Experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies.
• Knowledge in AI/ML accelerator or data center SoC design.
• Knowledge of scripting languages like Python or TCL for workflow automation.
• Experience with software-hardware co-design for end-to-end system optimization.