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Senior Principal Engineer – Verification – Ethernet – Serdes – Uvm
| Company | Marvell |
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| Location | Santa Clara, CA, USA |
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| Salary | $168920 – $253000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s, Master’s |
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| Experience Level | Expert or higher |
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Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
- 12+ years of industry experience in IP/SOC/ASIC verification with 3+ years of leading DV teams
- Strong verification expertise and hands-on experience with SystemVerilog and UVM
- Proficiency in various verification methodologies and demonstrable experience with industry-standard tools for verification, simulation, and emulation
- Extensive experience in verifying PCIE/Ethernet PHY protocols (e.g., Ethernet MAC, Ethernet Switch) and VIP is a plus.
- Experience with scripting languages such as Perl, Python.
- Solid understanding of digital design concepts and ASIC/FPGA design flow.
- Experience with DV test plan and coverage-driven constraint randomization testing
- Excellent cross-discipline communication and interpersonal skills
- Strong problem-solving abilities with keen attention to detail.
- Ability to work in a fast-paced, collaborative environment.
Responsibilities
- Develop and execute comprehensive verification plans for complex semiconductor designs, with a focus on High-Speed Serdes PHY/Ethernet functionality.
- Architect and implement advanced verification environments using SystemVerilog and Universal Verification Methodology (UVM).
- Design and develop reusable verification components and test benches to accelerate verification closure.
- Collaborate closely with cross-functional teams including design, architecture, and software teams to ensure seamless integration of verification strategies.
- Analyze and debug test failures to identify root causes and drive resolution.
- Lead and mentor junior team members and provide technical guidance to enhance team expertise.
Preferred Qualifications
- Hands-on experience with PHY/SERDES verification is advantageous.
- Previous experience in mentoring or leading verification teams.
- Knowledge of High Speed PHYs, Ethernet PHY, MAC, Interoperability, Clauses CL72/92/136/162/178, Serdes 112G/224G per lane
- Working with vendor Ethernet VIP’s and test suites
- MATLAB and C/C++ based system simulation and evaluation, Systems C, DPI-C
