Senior Principal Verification Engineer

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience. OR Master’s degree in Computer Science, Electrical Engineering or related fields with 10+ years of experience. OR PhD in Computer Science, Electrical Engineering or related fields with 8+ years of experience.
Strong background in SoC verification and test bench development using UVM, System Verilog, C/C++, and DPI.
Strong background in PCIe protocol and application with at least 5 years of experience working in design or verification in this area.
Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations, data structure).
Must have effective interpersonal and teamwork skills.
Participate in problem solving and quality improvement activities.
Demonstrate initiative and a bias for thoughtful action.
Grounded, detail-oriented, always backs up ideas with facts.
Must have the ability to define problems, issues and opportunities, analyze data, establish facts, and draw valid conclusions from various datasets.

Architect and implement simulation test bench in UVM.
Develop and execute test-plans for verifying correctness and performance of the design.
Own and debug failures in simulation to root-cause problems.
Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations.
Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.

No preferred qualifications provided.