Senior Staff Engineer – ASIC Design

Senior Staff Engineer – ASIC Design

Requirements

• BE (MS preferred) in Computer/Electrical Engineering or Computer Science with 15+ years working experiences in logic design, data center technologies, or cloud infrastructures.
• Experience in micro architecture of SoC, interface sub systems, logic modules.
• Good knowledge in ASIC design flow.
• Experience in the commercial IPs such as UCIe, CPU, Ethernet, and HBM interfaces.
• Deep understanding of PPA (performance, power, and area) trade-offs.
• Experience in complex logic designs and timing closure on the large sophisticated designs.
• Self-motivated problem-solver with an ability to work well in a team.

Responsibilities

• Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level.
• Responsible for logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA).
• Responsible for integrating the third part IPs with system bus, peripherals and CPU cores.
• Work closely with design verification team for debug, to meet code and functional coverage targets.
• Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.

Preferred Qualifications

• Experience and knowledge in HBM.
• Working knowledge of ARM processors, AMBA and AXI protocols.
• Experience and/or knowledge on compression, encryption algorithms.
• Experience and/or knowledge of the emerging technologies (CXL, Computation in memory and storage, Ethernet-attached SSD etc.) in server memory and storage systems.
• Highly motivated with good verbal and written communication skills.
• Creativity in problem solving.