Senior Staff Hardware Engineer Signal Integrity

Senior Staff Hardware Engineer Signal Integrity

Requirements

• Bachelor’s degree in Engineering, or any other related field with 6+ years of experience; or a Master’s degree or Ph.D. with 3+ years of experience with a proven track record of designs in high volume production.
• 5+ years of experience with HFSS simulations of PCB, packages and substrates for high speed interfaces (112G SerDes, PCIe Gen5)
• 5+ years of experience with DC IR drop and PDN analysis for boards with Cadence Sigrity and PowerDC.
• 5+ years of experience with layout tools like Allegro for design extraction.
• Possesses strong fundamentals in 3D/2D EM simulation tools and transmission line theory.
• Familiarity with electromagnetic compatibility (EMC) and electromagnetic interference (EMI) mitigation techniques.
• Excellent communication skills, both verbal and written, to effectively collaborate with cross-functional teams and present findings to stakeholders.

Responsibilities

• Perform simulations for signal integrity analysis.
• Perform hands-on high speed signal validation and analysis verification including material, de-embedding, and component characterization.
• Collaborate cross-functionally with hardware design, system architecture, silicon, and layout teams to optimize signal and power integrity design based on the simulation data and measurements.
• Power delivery modeling, simulation, and characterization for die, package, board, and voltage regulators.
• Provide implementation guidelines and feedback to silicon, package, and hardware design group for electrical signal and power integrity (crosstalk, return loss, jitter, EMI, power supply noise).
• PCB stackup review and layer assignment for High speed and PDN.
• Document engineering processes and procedures.

Preferred Qualifications

No preferred qualifications provided.