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Senior Test and Integration Engineer
| Company | Leidos |
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| Location | Halethorpe, MD, USA |
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| Salary | $126100 – $227950 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior, Expert or higher |
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Requirements
- Active TS/SCI w/ Polygraph
- Ten (10+) years of IA hardware testing and integration development experience and an Engineering or Computer Science Bachelor’s degree. An additional four (4) years of experience may be substituted for the education requirement.
- Ten (10+) years of experience in the following applicable programming languages: Java, Python, C/C++, RISC Assembly, Bash, Tcl/TK, and Verilog.
- Ten (10+) years of experience with GitLab, FPGA design, Xilinx’s Vivado, Microblaze Design Suite, and Partial Reconfiguration.
Responsibilities
- Prepare interactive Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) test benches.
- Write test scripts using “C” and “Tcl/TK” code languages.
- Conduct functional verification and testing of new ASIC designs prior to fabrication using Field Programmable Gate Arrays (FPGA) to emulate the chips.
- (U//FOUO) Write custom interfaces between Commercial off the Shelf (COTS) software and Mentor Graphics products.
- Use advanced verification methodologies using industry standard UVM (Unified Verification Methodology).
- Perform functional testing on variants, prototype devices and production versions of ASIC chip designs following production.
- Design in-depth security verification tests.
Preferred Qualifications
No preferred qualifications provided.
