SoC Design Verification Lead

SoC Design Verification Lead

Requirements

• Bachelor’s degree in Electrical or Computer Science Engineering or any related field with 6+ years of relevant experience
• Master’s degree in Electrical or Computer Science Engineering or any related field with 4+ years of relevant experience
• PhD in Electrical or Computer Science Engineering or any related field with 2+ years of relevant experience
• Relevant technical experience in Silicon Design and/or Validation/Verification

Responsibilities

• Performs functional logic verification of an integrated SoC to ensure design will meet specifications
• Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications
• Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs
• Replicates, root causes, and debugs issues in the pre-silicon environment
• Finds and implements corrective measures to resolve failing tests
• Collaborates and communicates with SoC architects, micro architects, full chip architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features
• Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
• Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage
• Maintains and improves existing functional verification infrastructure and methodology
• Absorbs learning from post silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products

Preferred Qualifications

• Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs
• Proficiency in UVM/SV constrained-random coverage-based design verification
• OVM/UVM, System Verilog, constrained random verification methodologies
• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure)
• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies
• UVM/SV Verification IP architecture, development and validation experience
• Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols – transaction layer, data link layer, and PHY layer
• Experience with one or more scripting languages to facilitate automation
• Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks
• Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market
• Experience in Xeon CPU Pre-Silicon or Post Silicon Validation

Benefits

No information provided on Benefits.