SoC Physical Design Engineer

Bachelor’s degree in electrical engineering, Computer Engineering or related field with 5+ years of relevant experience OR
Master’s degree Electrical Engineering, Computer Engineering or related field with 3+ years of relevant experience
Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools
Static timing analysis constraint understanding and generation, clock stamping, and timing closure
Multiple Power Domain analysis using standard Power Formats UPF or CPF

Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools.
Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF.
Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Participating in the development and improvement of physical design methodologies and flow automation.
Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs.