SoC Post-silicon Debug and Functional Validation Engineer
| Company | Intel |
|---|---|
| Location | Hillsboro, OR, USA, Folsom, CA, USA |
| Salary | $121050 – $170890 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Mid Level, Senior |
Requirements
- Bachelors with 2+ years’ experience or master’s degree in electrical engineering, Computer Engineering, Computer Science or related field.
- 1+ years’ experience hands-on experience in electrical or pre/post silicon validation.
- 1+ years of experience with electrical or silicon validation tools and lab equipment (e.g., logic analyzers, oscilloscopes), and debugging techniques.
- 1+ years of experience in scripting and programming languages (e.g., Python, C/C++, or Perl) to develop validation tools and frameworks (such as debuggers, analyzers, oscilloscope, jTag).
Responsibilities
- Develop and execute validation plans to verify CPU/SOC functionality, Power and thermal management across multiple silicon platforms.
- Design, implement, and debug validation tests and methodologies for post-silicon environments.
- Collaborate with cross-functional teams, including design, firmware, software, and manufacturing, to identify and resolve issues.
- Analyze and debug CPU/SOC and system-level issues using advanced tools and methodologies.
- Lead debug task forces to root-cause and resolve issues impacting program milestones.
- Mentor junior validation engineers to aid in their technical development.
- Drive validation automation, coverage improvement, and process efficiency for validation execution.
- Work with internal stakeholders to ensure smooth integration and delivery of products to the market.
Preferred Qualifications
- Candidates with advanced degrees and 5+ years’ experience encouraged to apply.
- Experience with power management, graphics, AI, Security, X86, and multimedia.
- Hands on experience with pre-silicon verification or Microarchitecture, particularly in CPU, SOC, or chipset domains.
- Familiarity with power and performance testing methodologies is plus.
- Experience with Intel architecture, silicon bring-up, and validation flow.
- Knowledge of firmware and software interaction with hardware.