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Sr. SoC Debug Engineer – Server – ASICS Engineering
| Company | Qualcomm |
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| Location | San Diego, CA, USA |
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| Salary | $164000 – $246000 |
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| Type | Full-Time |
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| Degrees | |
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| Experience Level | Senior, Expert or higher |
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Requirements
- 9+ years of experience with pre-si and post-silicon enabling, bring-up, analyze failures at the embedded platform level.
- RTL inspection and understanding of basic RTL
- Lead the effort for develop and implement solutions for faster debug at the platform level including isolating failing components of a system
- Creating debug strategies and plans for partners to more rapidly triage failures to isolate specific components including PVT and marginality issues.
- Debugging low level software and hardware issues
- Debug tools including JTAG
- Using Lab Equipment (Logic Analyzer, Scope, Signal Generator etc…)
Responsibilities
- Lead Bring up, debug, analyze failures at the embedded platform level in both pre-Si and post-Si phase
- Lead on initiatives for faster debug at the platform level including isolating failing components of a system
- Creating and leading debug strategies and plans for partners to more rapidly triage failures to isolate specific components including PVT and marginality issues.
- Perform real-time debugging and troubleshooting of server hardware, including motherboards, processors, memory, storage devices, power supplies, and networking components.
- Investigate manufacturing defects, determine root causes, and implement corrective actions to improve product quality and reliability
Preferred Qualifications
- Strong programming and scripting languages (C, Assembly, Perl, Python, etc.)
- Good understanding of power and performance
- Strong Knowledge of TCU, PVT, Fmax, Vmin test methodology and hands-on experience
- CPU and SoC architectures for Server/Compute/Mobile chipsets.
- Hands on experience in handling server specific use-cases including Server Boot Configuration and Server Reset Scenarios.
- Debug experience of Server Reboot stress scenarios including both Cold and Warm boot.
- Knowledge of multi-die secure boot flow and debugs involved in multi-die configuration
