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Sr. Staff CPU Physical Design CAD Engineer – CPU Engineering

Sr. Staff CPU Physical Design CAD Engineer – CPU Engineering

CompanyQualcomm
LocationSanta Clara, CA, USA
Salary$198700 – $298100
TypeFull-Time
DegreesBachelor’s, Master’s, PhD
Experience LevelSenior, Expert or higher

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • OR Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Responsibilities

  • Develop, integrate and release new features in our high-performance place-and-route CAD flow
  • Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
  • Maintain, support and debug implementation flows, and resolve project-specific issues
  • Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA.
  • Work with EDA vendors to define roadmap and to resolve tool issues

Preferred Qualifications

  • Masters degree in Electrical/Electronics Engineering or Computer Science
  • Ten+ years of hands-on experience in place-and-route of high-performance chips – either in a design or CAD role
  • High level of proficiency in Tcl as well as Python
  • Experience with automation
  • Experience with a wide variety of Physical Design tasks – ranging all the way from place-and-route, analysis, timing sign-off and PDV
  • Experience with advanced technology nodes (5nm or lower)
  • Solid understanding of digital design, timing analysis and physical verification
  • Strong user of industry-standard place-and-route tools such as Cadence Innovus
  • Proven track record of managing and regressing place-and-route flows

Benefits

    No information provided on Benefits.