System Memory Performance and Power Engineer

BS or MS degree in EE/CE or equivalent experience.
8+ years of experience in memory interface or subsystem architecture, design, and validation.
Strong fundamentals in EE, digital/analog design, signal integrity, low power design, timing analysis, and architecture.
A deep understanding of system-level memory interaction with different IPs and SW/FW is crucial.
Validated hands-on lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers).
Excellent problem-solving, teamwork, and interpersonal skills.

Build roadmaps of memory system-level features to address low power, low noise, perf/watt efficient, and stable/reliable product needs by doing prototyping, use case analysis, and system level cost/benefit tradeoff.
Architect, design, and integrate memory system-level features, controllers, and policies based on the roadmap to optimize product performance, power, and reliability/stability.
Collaborate with architecture, ASIC, board/platform design, software/firmware, marketing, and other multi-functional teams to drive architecture, design, and debug.
Keep track of the latest industry direction, market needs, and technology development; incorporate them into future roadmaps to build more competitive products.
Lead debug, craft WARs, and supporting bringup, validation, manufacturing, and customer issues on relevant features.

Experience with control systems, boot/reset flows, micro-architecture, and system architecture is highly valuable.
Experience with Python, Perl, C/C++, Windows, and Linux is a plus.