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TPU Silicon Validation Engineer
Company | Google |
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Location | Sunnyvale, CA, USA |
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Salary | $132000 – $189000 |
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Type | Full-Time |
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Degrees | Bachelor’s |
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Experience Level | Junior, Mid Level |
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Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience scripting in Python or equivalent programming language.
- Experience in bringing up ASICs, performing functional and performance validation, and debugging failures.
Responsibilities
- Develop detailed silicon test plans, based on design specifications and coordination with a cross-functional silicon team (architecture, design, software, firmware) for Google’s Tensor Processing Units.
- Implement these test plans by developing software tests and flows for system validation and verification, in addition to driving the creation of some of these tests by others.
- Endeavor to triage and debug issues found during new product development and find solutions.
- Develop and execute test plans for functional and performance validation.
- Collaborate with system software and software test infrastructure developers to ensure we have proper ASIC test coverage for an entire program.
- Help develop a common set of requirements, processes, and tests to ensure smooth and reliable performance of ASIC projects.
- Work throughout the entire project lifecycle, from early pre-silicon planning and test development, through end-of-life characterization and failure debug.
- Develop and operate software-based tests for full investigation of ASIC operation.
- Work closely with both hardware and software teams to successfully validate designs, and to identify design issues.
Preferred Qualifications
- Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
- 2 years of experience with C++/Python software design principles.
- Experience bringing up high-power ASICs.
- Experience with reading hardware description languages (SystemVerilog) and chip design flow, and building test automation tools and scripts.
- Enthusiasm for unusual computer architectures.
Benefits
No information provided on Benefits.