Validation Engineer – Staff
| Company | d-Matrix |
|---|---|
| Location | Santa Clara, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s |
| Experience Level | Senior, Expert or higher |
Requirements
- BS/MS in Electrical/Computer Engineering with 12 + years industry experience post-Si validation with at least 3-5 years as a lead/manager.
- Familiarity with high speed serial protocol (such as PCIe Gen3/4/5) and/or high speed external memory technology (such as LPDDR3/LPDDR4/LPDDR5 and/or high speed I/O standards.
- Experienced with PLLs, Si bring up and familiarity with Lab equipment (such as Oscilloscopes, pattern generator, logic analyzer etc)
- Excellent debugging verbal and written communication skills
- Capable of working effectively across cross functional organizational boundaries.
- Leader with a passion for successful products and capable of driving team direction and bring up strategy.
Responsibilities
- Work on chip(s) bring up, Validation and debug of a cutting edge interference accelerator chiplet.
- Create and execute on test bring up and detailed validation plan as well as test automation (wherever applicable) with the team.
- Build tests scripts for host systems to test various validation aspects of high speed interface(s) such as PCIe, and/or LPDDR, and/or D2D.
- Work with the team on procuring/acquiring lab equipment.
- Collaborate with hardware, software and operations team on various aspects (such as ATE tests, hardware/software debug etc.)
Preferred Qualifications
-
No preferred qualifications provided.