Yield Failure Analysis Module Engineer

Yield Failure Analysis Module Engineer

Requirements

• Candidate must possess a Bachelor’s degree in Electrical Engineering, Physics, Materials Science or related STEM field of study with +5 years of related experience.
• 1+ years of relevant experience in understanding and/or practical experience with semiconductor device physics and contemporary fabrication process technologies.
• 1+ years of relevant experience in understanding and/or practical experience with materials, surface and device characterization techniques supporting semiconductor science and manufacturing (such as SEM, TEM, EDX, SIMS, XPS, XRD, FTIR or Auger).
• Candidate must be willing to travel for training assignments to one of Intel’s manufacturing development sites.
• US citizenship required.
• Ability to obtain and maintain a US Government Security Clearance.

Responsibilities

• Conduct failure analysis and root cause determination on the latest technologies and products in high-volume manufacturing at Intel.
• Generate yield improvement outcomes from the results of the analysis in partnership with Yield and Process engineering.
• Lead and direct the analysis through various modules of the failure analysis lab – from job submission to reporting the final results and executing corrective action.

Preferred Qualifications

• Master’s degree in Electrical Engineering, Physics, Materials Science or related STEM field with +3 years of related experience, or a Ph.D. in the previously mentioned areas.
• Materials and Sample Preparation methods such as polishing, dimpling, wet/dry etches.
• SEM, FIB, TEM, LSM (electron, ion, photon beam tools) operation and theory.
• TEM sample preparation.
• Fault isolation methods such as: Emission Microscopy (thermal, NIR or optical), TIVA/LIVA/OBIRCH/EBIRCH, LVP, LADA, SMI, lock-in thermography etc.
• Lab bench or ATE testing capabilities for SoC/CPU.
• Hands-on experience with electrical device probing and characterization, particularly with atomic force or beam-based methods after some deprocessing/delayering. This should include the ability to isolate key defective aspects of device and interconnect characteristics and convey the next steps of analysis to the team and customers.
• Experience or background with semiconductor product EDA tools, CAD navigation, testing platforms and test plans.
• Skills to design and code automation for lab testing/characterization using modern scripting or software development tools – such as Python, Perl/TCL, JSL, R or similar.
• Exposure to or strong background using statistical analysis tools such as JMP, SAS, Minitab.
• Familiarity with latest machine learning tools applied to process and device analysis to accelerate root cause determination.
• Understanding or training in SoC or CPU microarchitecture and testing.
• Practical or applied lab research is preferred.
• Prior experience working with US Government contracts including security and sensitive document handling.
• Active US Government Security Clearance, with a minimum of Secret level.